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Commit 0acefdbe authored by Carlos Eduardo Seo's avatar Carlos Eduardo Seo Committed by David Chase
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cmd/asm, cmd/internal/obj/ppc64: Add vector scalar (VSX) registers and instructions 

The current implementation for Power architecture does not include the vector
scalar (VSX) registers.  This adds the 63 VSX registers and the most commonly
used instructions: load/store VSX vector/scalar, move to/from VSR, logical
operations, select, merge, splat, permute, shift, FP-FP conversion, FP-integer
conversion and integer-FP conversion.

Change-Id: I0f7572d2359fe7f3ea0124a1eb1b0bebab33649e
Reviewed-on: https://go-review.googlesource.com/30510Reviewed-by: 's avatarLynn Boger <laboger@linux.vnet.ibm.com>
Reviewed-by: 's avatarDavid Chase <drchase@google.com>
Run-TryBot: David Chase <drchase@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
parent 9c02c756
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Inline Side-by-side
Showing with 440 additions and 1 deletion
src/cmd/asm/internal/arch/arch.go
View file @ 0acefdbe
...@@ -322,6 +322,9 @@ func archPPC64() *Arch { ...@@ -322,6 +322,9 @@ func archPPC64() *Arch {
for i := ppc64.REG_V0; i <= ppc64.REG_V31; i++ { for i := ppc64.REG_V0; i <= ppc64.REG_V31; i++ {
register[obj.Rconv(i)] = int16(i) register[obj.Rconv(i)] = int16(i)
} }
for i := ppc64.REG_VS0; i <= ppc64.REG_VS63; i++ {
register[obj.Rconv(i)] = int16(i)
}
for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ { for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ {
register[obj.Rconv(i)] = int16(i) register[obj.Rconv(i)] = int16(i)
} }
......
src/cmd/asm/internal/arch/ppc64.go
View file @ 0acefdbe
...@@ -77,6 +77,10 @@ func ppc64RegisterNumber(name string, n int16) (int16, bool) { ...@@ -77,6 +77,10 @@ func ppc64RegisterNumber(name string, n int16) (int16, bool) {
if 0 <= n && n <= 7 { if 0 <= n && n <= 7 {
return ppc64.REG_CR0 + n, true return ppc64.REG_CR0 + n, true
} }
case "VS":
if 0 <= n && n <= 63 {
return ppc64.REG_VS0 + n, true
}
case "V": case "V":
if 0 <= n && n <= 31 { if 0 <= n && n <= 31 {
return ppc64.REG_V0 + n, true return ppc64.REG_V0 + n, true
......
src/cmd/asm/internal/asm/operand_test.go
View file @ 0acefdbe
...@@ -340,6 +340,70 @@ var ppc64OperandTests = []operandTest{ ...@@ -340,6 +340,70 @@ var ppc64OperandTests = []operandTest{
{"6(PC)", "6(PC)"}, {"6(PC)", "6(PC)"},
{"CR7", "CR7"}, {"CR7", "CR7"},
{"CTR", "CTR"}, {"CTR", "CTR"},
{"VS0", "VS0"},
{"VS1", "VS1"},
{"VS2", "VS2"},
{"VS3", "VS3"},
{"VS4", "VS4"},
{"VS5", "VS5"},
{"VS6", "VS6"},
{"VS7", "VS7"},
{"VS8", "VS8"},
{"VS9", "VS9"},
{"VS10", "VS10"},
{"VS11", "VS11"},
{"VS12", "VS12"},
{"VS13", "VS13"},
{"VS14", "VS14"},
{"VS15", "VS15"},
{"VS16", "VS16"},
{"VS17", "VS17"},
{"VS18", "VS18"},
{"VS19", "VS19"},
{"VS20", "VS20"},
{"VS21", "VS21"},
{"VS22", "VS22"},
{"VS23", "VS23"},
{"VS24", "VS24"},
{"VS25", "VS25"},
{"VS26", "VS26"},
{"VS27", "VS27"},
{"VS28", "VS28"},
{"VS29", "VS29"},
{"VS30", "VS30"},
{"VS31", "VS31"},
{"VS32", "VS32"},
{"VS33", "VS33"},
{"VS34", "VS34"},
{"VS35", "VS35"},
{"VS36", "VS36"},
{"VS37", "VS37"},
{"VS38", "VS38"},
{"VS39", "VS39"},
{"VS40", "VS40"},
{"VS41", "VS41"},
{"VS42", "VS42"},
{"VS43", "VS43"},
{"VS44", "VS44"},
{"VS45", "VS45"},
{"VS46", "VS46"},
{"VS47", "VS47"},
{"VS48", "VS48"},
{"VS49", "VS49"},
{"VS50", "VS50"},
{"VS51", "VS51"},
{"VS52", "VS52"},
{"VS53", "VS53"},
{"VS54", "VS54"},
{"VS55", "VS55"},
{"VS56", "VS56"},
{"VS57", "VS57"},
{"VS58", "VS58"},
{"VS59", "VS59"},
{"VS60", "VS60"},
{"VS61", "VS61"},
{"VS62", "VS62"},
{"VS63", "VS63"},
{"V0", "V0"}, {"V0", "V0"},
{"V1", "V1"}, {"V1", "V1"},
{"V2", "V2"}, {"V2", "V2"},
......
src/cmd/asm/internal/asm/testdata/ppc64.s
View file @ 0acefdbe
...@@ -677,7 +677,7 @@ label1: ...@@ -677,7 +677,7 @@ label1:
// Described as: // Described as:
// <instruction type>, <instruction format> // <instruction type>, <instruction format>
// <golang asm operand order> produces // <go asm operand order> produces
// <Power ISA operand order> // <Power ISA operand order>
// Vector load, VX-form // Vector load, VX-form
...@@ -880,6 +880,139 @@ label1: ...@@ -880,6 +880,139 @@ label1:
VSHASIGMAW $15, V1, $1, V0 VSHASIGMAW $15, V1, $1, V0
VSHASIGMAD $15, V1, $1, V0 VSHASIGMAD $15, V1, $1, V0
// VSX instructions
// Described as:
// <instruction type>, <instruction format>
// <go asm operand order> produces
// <Power ISA operand order>
// VSX load, XX1-form
// <MNEMONIC> (RB)(RA*1),XT produces
// <mnemonic> XT,RA,RB
LXVD2X (R1)(R2*1), VS0
LXVDSX (R1)(R2*1), VS0
LXVW4X (R1)(R2*1), VS0
LXSDX (R1)(R2*1), VS0
LXSIWAX (R1)(R2*1), VS0
LXSIWZX (R1)(R2*1), VS0
// VSX store, XX1-form
// <MNEMONIC> XS,(RB)(RA*1) produces
// <mnemonic> XS,RA,RB
STXVD2X VS63, (R1)(R2*1)
STXVW4X VS63, (R1)(R2*1)
STXSDX VS63, (R1)(R2*1)
STXSIWX VS63, (R1)(R2*1)
// VSX move from VSR, XX1-form
// <MNEMONIC> XS,RA produces
// <mnemonic> RA,XS
MFVSRD VS0, R1
MFVSRWZ VS33, R1
// VSX move to VSR, XX1-form
// <MNEMONIC> RA,XT produces
// <mnemonic> XT,RA
MTVSRD R1, VS0
MTVSRWA R1, VS31
MTVSRWZ R1, VS63
// VSX AND, XX3-form
// <MNEMONIC> XA,XB,XT produces
// <mnemonic> XT,XA,XB
XXLANDQ VS0,VS1,VS32
XXLANDC VS0,VS1,VS32
XXLEQV VS0,VS1,VS32
XXLNAND VS0,VS1,VS32
// VSX OR, XX3-form
// <MNEMONIC> XA,XB,XT produces
// <mnemonic> XT,XA,XB
XXLORC VS0,VS1,VS32
XXLNOR VS0,VS1,VS32
XXLORQ VS0,VS1,VS32
XXLXOR VS0,VS1,VS32
// VSX select, XX4-form
// <MNEMONIC> XA,XB,XC,XT produces
// <mnemonic> XT,XA,XB,XC
XXSEL VS0,VS1,VS3,VS32
// VSX merge, XX3-form
// <MNEMONIC> XA,XB,XT produces
// <mnemonic> XT,XA,XB
XXMRGHW VS0,VS1,VS32
XXMRGLW VS0,VS1,VS32
// VSX splat, XX2-form
// <MNEMONIC> XB,UIM,XT produces
// <mnemonic> XT,XB,UIM
XXSPLTW VS0,$3,VS32
// VSX permute, XX3-form
// <MNEMONIC> XA,XB,DM,XT produces
// <mnemonic> XT,XA,XB,DM
XXPERMDI VS0,VS1,$3,VS32
// VSX shift, XX3-form
// <MNEMONIC> XA,XB,SHW,XT produces
// <mnemonic> XT,XA,XB,SHW
XXSLDWI VS0,VS1,$3,VS32
// VSX scalar FP-FP conversion, XX2-form
// <MNEMONIC> XB,XT produces
// <mnemonic> XT,XB
XSCVDPSP VS0,VS32
XSCVSPDP VS0,VS32
XSCVDPSPN VS0,VS32
XSCVSPDPN VS0,VS32
// VSX vector FP-FP conversion, XX2-form
// <MNEMONIC> XB,XT produces
// <mnemonic> XT,XB
XVCVDPSP VS0,VS32
XVCVSPDP VS0,VS32
// VSX scalar FP-integer conversion, XX2-form
// <MNEMONIC> XB,XT produces
// <mnemonic> XT,XB
XSCVDPSXDS VS0,VS32
XSCVDPSXWS VS0,VS32
XSCVDPUXDS VS0,VS32
XSCVDPUXWS VS0,VS32
// VSX scalar integer-FP conversion, XX2-form
// <MNEMONIC> XB,XT produces
// <mnemonic> XT,XB
XSCVSXDDP VS0,VS32
XSCVUXDDP VS0,VS32
XSCVSXDSP VS0,VS32
XSCVUXDSP VS0,VS32
// VSX vector FP-integer conversion, XX2-form
// <MNEMONIC> XB,XT produces
// <mnemonic> XT,XB
XVCVDPSXDS VS0,VS32
XVCVDPSXWS VS0,VS32
XVCVDPUXDS VS0,VS32
XVCVDPUXWS VS0,VS32
XVCVSPSXDS VS0,VS32
XVCVSPSXWS VS0,VS32
XVCVSPUXDS VS0,VS32
XVCVSPUXWS VS0,VS32
// VSX scalar integer-FP conversion, XX2-form
// <MNEMONIC> XB,XT produces
// <mnemonic> XT,XB
XVCVSXDDP VS0,VS32
XVCVSXWDP VS0,VS32
XVCVUXDDP VS0,VS32
XVCVUXWDP VS0,VS32
XVCVSXDSP VS0,VS32
XVCVSXWSP VS0,VS32
XVCVUXDSP VS0,VS32
XVCVUXWSP VS0,VS32
// //
// NOP // NOP
// //
......
src/cmd/internal/obj/ppc64/a.out.go
View file @ 0acefdbe
...@@ -44,6 +44,8 @@ const ( ...@@ -44,6 +44,8 @@ const (
) )
const ( const (
/* RBasePPC64 = 4096 */
/* R0=4096 ... R31=4127 */
REG_R0 = obj.RBasePPC64 + iota REG_R0 = obj.RBasePPC64 + iota
REG_R1 REG_R1
REG_R2 REG_R2
...@@ -77,6 +79,7 @@ const ( ...@@ -77,6 +79,7 @@ const (
REG_R30 REG_R30
REG_R31 REG_R31
/* F0=4128 ... F31=4159 */
REG_F0 REG_F0
REG_F1 REG_F1
REG_F2 REG_F2
...@@ -110,6 +113,7 @@ const ( ...@@ -110,6 +113,7 @@ const (
REG_F30 REG_F30
REG_F31 REG_F31
/* V0=4160 ... V31=4191 */
REG_V0 REG_V0
REG_V1 REG_V1
REG_V2 REG_V2
...@@ -143,6 +147,72 @@ const ( ...@@ -143,6 +147,72 @@ const (
REG_V30 REG_V30
REG_V31 REG_V31
/* VS0=4192 ... VS63=4255 */
REG_VS0
REG_VS1
REG_VS2
REG_VS3
REG_VS4
REG_VS5
REG_VS6
REG_VS7
REG_VS8
REG_VS9
REG_VS10
REG_VS11
REG_VS12
REG_VS13
REG_VS14
REG_VS15
REG_VS16
REG_VS17
REG_VS18
REG_VS19
REG_VS20
REG_VS21
REG_VS22
REG_VS23
REG_VS24
REG_VS25
REG_VS26
REG_VS27
REG_VS28
REG_VS29
REG_VS30
REG_VS31
REG_VS32
REG_VS33
REG_VS34
REG_VS35
REG_VS36
REG_VS37
REG_VS38
REG_VS39
REG_VS40
REG_VS41
REG_VS42
REG_VS43
REG_VS44
REG_VS45
REG_VS46
REG_VS47
REG_VS48
REG_VS49
REG_VS50
REG_VS51
REG_VS52
REG_VS53
REG_VS54
REG_VS55
REG_VS56
REG_VS57
REG_VS58
REG_VS59
REG_VS60
REG_VS61
REG_VS62
REG_VS63
REG_CR0 REG_CR0
REG_CR1 REG_CR1
REG_CR2 REG_CR2
...@@ -264,6 +334,7 @@ const ( ...@@ -264,6 +334,7 @@ const (
C_REG C_REG
C_FREG C_FREG
C_VREG C_VREG
C_VSREG
C_CREG C_CREG
C_SPR /* special processor register */ C_SPR /* special processor register */
C_ZCON C_ZCON
...@@ -781,6 +852,87 @@ const ( ...@@ -781,6 +852,87 @@ const (
AVSHASIGMAW AVSHASIGMAW
AVSHASIGMAD AVSHASIGMAD
/* VSX */
ALXV
ALXVD2X
ALXVDSX
ALXVW4X
ASTXV
ASTXVD2X
ASTXVW4X
ALXS
ALXSDX
ASTXS
ASTXSDX
ALXSI
ALXSIWAX
ALXSIWZX
ASTXSI
ASTXSIWX
AMFVSR
AMFVSRD
AMFVSRWZ
AMTVSR
AMTVSRD
AMTVSRWA
AMTVSRWZ
AXXLAND
AXXLANDQ
AXXLANDC
AXXLEQV
AXXLNAND
AXXLOR
AXXLORC
AXXLNOR
AXXLORQ
AXXLXOR
AXXSEL
AXXMRG
AXXMRGHW
AXXMRGLW
AXXSPLT
AXXSPLTW
AXXPERM
AXXPERMDI
AXXSI
AXXSLDWI
AXSCV
AXSCVDPSP
AXSCVSPDP
AXSCVDPSPN
AXSCVSPDPN
AXVCV
AXVCVDPSP
AXVCVSPDP
AXSCVX
AXSCVDPSXDS
AXSCVDPSXWS
AXSCVDPUXDS
AXSCVDPUXWS
AXSCVXP
AXSCVSXDDP
AXSCVUXDDP
AXSCVSXDSP
AXSCVUXDSP
AXVCVX
AXVCVDPSXDS
AXVCVDPSXWS
AXVCVDPUXDS
AXVCVDPUXWS
AXVCVSPSXDS
AXVCVSPSXWS
AXVCVSPUXDS
AXVCVSPUXWS
AXVCVXP
AXVCVSXDDP
AXVCVSXWDP
AXVCVUXDDP
AXVCVUXWDP
AXVCVSXDSP
AXVCVSXWSP
AXVCVUXDSP
AXVCVUXWSP
ALAST ALAST
// aliases // aliases
......
src/cmd/internal/obj/ppc64/anames.go
View file @ 0acefdbe
...@@ -466,5 +466,84 @@ var Anames = []string{ ...@@ -466,5 +466,84 @@ var Anames = []string{
"VSHASIGMA", "VSHASIGMA",
"VSHASIGMAW", "VSHASIGMAW",
"VSHASIGMAD", "VSHASIGMAD",
"LXV",
"LXVD2X",
"LXVDSX",
"LXVW4X",
"STXV",
"STXVD2X",
"STXVW4X",
"LXS",
"LXSDX",
"STXS",
"STXSDX",
"LXSI",
"LXSIWAX",
"LXSIWZX",
"STXSI",
"STXSIWX",
"MFVSR",
"MFVSRD",
"MFVSRWZ",
"MTVSR",
"MTVSRD",
"MTVSRWA",
"MTVSRWZ",
"XXLAND",
"XXLANDQ",
"XXLANDC",
"XXLEQV",
"XXLNAND",
"XXLOR",
"XXLORC",
"XXLNOR",
"XXLORQ",
"XXLXOR",
"XXSEL",
"XXMRG",
"XXMRGHW",
"XXMRGLW",
"XXSPLT",
"XXSPLTW",
"XXPERM",
"XXPERMDI",
"XXSI",
"XXSLDWI",
"XSCV",
"XSCVDPSP",
"XSCVSPDP",
"XSCVDPSPN",
"XSCVSPDPN",
"XVCV",
"XVCVDPSP",
"XVCVSPDP",
"XSCVX",
"XSCVDPSXDS",
"XSCVDPSXWS",
"XSCVDPUXDS",
"XSCVDPUXWS",
"XSCVXP",
"XSCVSXDDP",
"XSCVUXDDP",
"XSCVSXDSP",
"XSCVUXDSP",
"XVCVX",
"XVCVDPSXDS",
"XVCVDPSXWS",
"XVCVDPUXDS",
"XVCVDPUXWS",
"XVCVSPSXDS",
"XVCVSPSXWS",
"XVCVSPUXDS",
"XVCVSPUXWS",
"XVCVXP",
"XVCVSXDDP",
"XVCVSXWDP",
"XVCVUXDDP",
"XVCVUXWDP",
"XVCVSXDSP",
"XVCVSXWSP",
"XVCVUXDSP",
"XVCVUXWSP",
"LAST", "LAST",
} }
src/cmd/internal/obj/ppc64/anames9.go
View file @ 0acefdbe
...@@ -9,6 +9,7 @@ var cnames9 = []string{ ...@@ -9,6 +9,7 @@ var cnames9 = []string{
"REG", "REG",
"FREG", "FREG",
"VREG", "VREG",
"VSREG",
"CREG", "CREG",
"SPR", "SPR",
"ZCON", "ZCON",
......
src/cmd/internal/obj/ppc64/asm9.go
View file @ 0acefdbe
This diff is collapsed.
src/cmd/internal/obj/ppc64/list9.go
View file @ 0acefdbe
...@@ -56,6 +56,9 @@ func Rconv(r int) string { ...@@ -56,6 +56,9 @@ func Rconv(r int) string {
if REG_V0 <= r && r <= REG_V31 { if REG_V0 <= r && r <= REG_V31 {
return fmt.Sprintf("V%d", r-REG_V0) return fmt.Sprintf("V%d", r-REG_V0)
} }
if REG_VS0 <= r && r <= REG_VS63 {
return fmt.Sprintf("VS%d", r-REG_VS0)
}
if REG_CR0 <= r && r <= REG_CR7 { if REG_CR0 <= r && r <= REG_CR7 {
return fmt.Sprintf("CR%d", r-REG_CR0) return fmt.Sprintf("CR%d", r-REG_CR0)
} }
......
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