Commit 76a763e0 authored by Russ Cox's avatar Russ Cox

8 shift bug

R=ken
OCL=32882
CL=32882
parent c30d81bd
...@@ -499,6 +499,18 @@ ret: ...@@ -499,6 +499,18 @@ ret:
; ;
} }
int
samereg(Node *a, Node *b)
{
if(a->op != OREGISTER)
return 0;
if(b->op != OREGISTER)
return 0;
if(a->val.u.reg != b->val.u.reg)
return 0;
return 1;
}
/* /*
* generate division. * generate division.
* caller must set: * caller must set:
...@@ -581,7 +593,7 @@ cgen_div(int op, Node *nl, Node *nr, Node *res) ...@@ -581,7 +593,7 @@ cgen_div(int op, Node *nl, Node *nr, Node *res)
void void
cgen_shift(int op, Node *nl, Node *nr, Node *res) cgen_shift(int op, Node *nl, Node *nr, Node *res)
{ {
Node n1, n2; Node n1, n2, cx, oldcx;
int a, w; int a, w;
Prog *p1; Prog *p1;
uvlong sc; uvlong sc;
...@@ -611,9 +623,19 @@ cgen_shift(int op, Node *nl, Node *nr, Node *res) ...@@ -611,9 +623,19 @@ cgen_shift(int op, Node *nl, Node *nr, Node *res)
return; return;
} }
memset(&oldcx, 0, sizeof oldcx);
nodreg(&cx, types[TUINT32], D_CX);
if(reg[D_CX] > 0 && !samereg(&cx, res)) {
regalloc(&oldcx, types[TUINT32], N);
gmove(&cx, &oldcx);
}
nodreg(&n1, types[TUINT32], D_CX); nodreg(&n1, types[TUINT32], D_CX);
regalloc(&n1, nr->type, &n1); // to hold the shift type in CX regalloc(&n1, nr->type, &n1); // to hold the shift type in CX
if(samereg(&cx, res))
regalloc(&n2, nl->type, N);
else
regalloc(&n2, nl->type, res); regalloc(&n2, nl->type, res);
if(nl->ullman >= nr->ullman) { if(nl->ullman >= nr->ullman) {
cgen(nl, &n2); cgen(nl, &n2);
...@@ -634,6 +656,11 @@ cgen_shift(int op, Node *nl, Node *nr, Node *res) ...@@ -634,6 +656,11 @@ cgen_shift(int op, Node *nl, Node *nr, Node *res)
patch(p1, pc); patch(p1, pc);
gins(a, &n1, &n2); gins(a, &n1, &n2);
if(oldcx.op != 0) {
gmove(&oldcx, &cx);
regfree(&oldcx);
}
gmove(&n2, res); gmove(&n2, res);
regfree(&n1); regfree(&n1);
......
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