Commit 8f53bc06 authored by Ken Thompson's avatar Ken Thompson

new convention, direction bit is

always left cleared. changed
compiler generated memcpy and
memset to assume CLD.

R=r
OCL=21215
CL=21215
parent ae5a475e
...@@ -874,22 +874,29 @@ sgen(Node *n, Node *ns, int32 w) ...@@ -874,22 +874,29 @@ sgen(Node *n, Node *ns, int32 w)
gins(AREP, N, N); // repeat gins(AREP, N, N); // repeat
gins(AMOVSQ, N, N); // MOVQ *(SI)-,*(DI)- gins(AMOVSQ, N, N); // MOVQ *(SI)-,*(DI)-
} }
// for future optimization
// we leave with the flag clear // we leave with the flag clear
gins(ACLD, N, N); gins(ACLD, N, N);
} else { } else {
// normal direction // normal direction
gins(ACLD, N, N); // clear direction flag if(q >= 4) {
if(q > 0) {
gconreg(AMOVQ, q, D_CX); gconreg(AMOVQ, q, D_CX);
gins(AREP, N, N); // repeat gins(AREP, N, N); // repeat
gins(AMOVSQ, N, N); // MOVQ *(SI)+,*(DI)+ gins(AMOVSQ, N, N); // MOVQ *(SI)+,*(DI)+
} else
while(q > 0) {
gins(AMOVSQ, N, N); // MOVQ *(SI)+,*(DI)+
q--;
} }
if(c > 0) { if(c >= 4) {
gconreg(AMOVQ, c, D_CX); gconreg(AMOVQ, c, D_CX);
gins(AREP, N, N); // repeat gins(AREP, N, N); // repeat
gins(AMOVSB, N, N); // MOVB *(SI)+,*(DI)+ gins(AMOVSB, N, N); // MOVB *(SI)+,*(DI)+
} else
while(c > 0) {
gins(AMOVSB, N, N); // MOVB *(SI)+,*(DI)+
c--;
} }
} }
} }
...@@ -1037,7 +1037,7 @@ cgen_as(Node *nl, Node *nr, int op) ...@@ -1037,7 +1037,7 @@ cgen_as(Node *nl, Node *nr, int op)
{ {
Node nc, n1; Node nc, n1;
Type *tl; Type *tl;
uint32 w, c; uint32 w, c, q;
int iszer; int iszer;
if(nl == N) if(nl == N)
...@@ -1058,31 +1058,32 @@ cgen_as(Node *nl, Node *nr, int op) ...@@ -1058,31 +1058,32 @@ cgen_as(Node *nl, Node *nr, int op)
if(debug['g']) if(debug['g'])
dump("\nclearfat", nl); dump("\nclearfat", nl);
if(nl->type->width < 0)
fatal("clearfat %T %lld", nl->type, nl->type->width);
w = nl->type->width; w = nl->type->width;
c = w % 8; // bytes
q = w / 8; // quads
if(w > 0)
gconreg(AMOVQ, 0, D_AX); gconreg(AMOVQ, 0, D_AX);
if(w > 0) {
nodreg(&n1, types[tptr], D_DI); nodreg(&n1, types[tptr], D_DI);
agen(nl, &n1); agen(nl, &n1);
gins(ACLD, N, N); // clear direction flag
}
c = w / 8; if(q >= 4) {
if(c > 0) { gconreg(AMOVQ, q, D_CX);
gconreg(AMOVQ, c, D_CX);
gins(AREP, N, N); // repeat gins(AREP, N, N); // repeat
gins(ASTOSQ, N, N); // STOQ AL,*(DI)+ gins(ASTOSQ, N, N); // STOQ AL,*(DI)+
} else
while(q > 0) {
gins(ASTOSQ, N, N); // STOQ AL,*(DI)+
q--;
} }
c = w % 8; if(c >= 4) {
if(c > 0) {
gconreg(AMOVQ, c, D_CX); gconreg(AMOVQ, c, D_CX);
gins(AREP, N, N); // repeat gins(AREP, N, N); // repeat
gins(ASTOSB, N, N); // STOB AL,*(DI)+ gins(ASTOSB, N, N); // STOB AL,*(DI)+
} else
while(c > 0) {
gins(ASTOSB, N, N); // STOB AL,*(DI)+
c--;
} }
goto ret; goto ret;
} }
......
...@@ -26,6 +26,7 @@ TEXT _rt0_amd64(SB),7,$-8 ...@@ -26,6 +26,7 @@ TEXT _rt0_amd64(SB),7,$-8
MOVQ AX, 0(R15) // 0(R15) is stack limit (w 104b guard) MOVQ AX, 0(R15) // 0(R15) is stack limit (w 104b guard)
MOVQ SP, 8(R15) // 8(R15) is base MOVQ SP, 8(R15) // 8(R15) is base
CLD // convention is D is always left cleared
CALL check(SB) CALL check(SB)
MOVL 16(SP), AX // copy argc MOVL 16(SP), AX // copy argc
......
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