The racewalk code was not updated for the new write barriers.
Make it more future-proof.

The new write barrier code assumed that +1 pointer would
be aligned properly for any type that might follow, but that's
not true on 32-bit systems where some types are 64-bit aligned.
The only system like that today is nacl/amd64p32.
Insert a dummy pointer so that the ambiguously typed
value is at +2 pointers, which is always max-aligned.

LGTM=r
R=r
CC=golang-codereviews, iant, khr
https://golang.org/cl/158890046