cmd/5c, cmd/5a, cmd/5l: ARM support for PREFETCH built-in

R=rsc
CC=golang-dev
https://golang.org/cl/6174049

src/cmd/5a/a.y

@@ -304,7 +304,7 @@ inst:
 /*
  * PLD
  */
-|	LTYPEPLD reg
+|	LTYPEPLD oreg
 	{
 		outcode($1, Always, &$2, NREG, &nullgen);
 	}

src/cmd/5c/peep.c

@@ -1067,6 +1067,7 @@ copyu(Prog *p, Adr *v, Adr *s)
 	case ABLT:
 	case ABGT:
 	case ABLE:
+	case APLD:
 		if(s != A) {
 			if(copysub(&p->from, v, s, 1))
 				return 1;

src/cmd/5c/reg.c

@@ -190,6 +190,14 @@ regopt(Prog *p)
 				r->set.b[z] |= bit.b[z];
 			break;
 
+		/*
+		 * right side read
+		 */
+		case APLD:
+			for(z=0; z<BITS; z++)
+				r->use2.b[z] |= bit.b[z];
+			break;
+
 		/*
 		 * funny
 		 */

src/cmd/5c/txt.c

@@ -1197,7 +1197,13 @@ gpseudo(int a, Sym *s, Node *n)
 void
 gprefetch(Node *n)
 {
-	// nothing
+	Node n1;
+
+	regalloc(&n1, n, Z);
+	gmove(n, &n1);
+	n1.op = OINDREG;
+	gins(APLD, &n1, Z);
+	regfree(&n1);
 }
 
 int

src/cmd/5l/asm.c

@@ -1429,9 +1429,14 @@ if(debug['G']) print("%ux: %s: arm %d\n", (uint32)(p->pc), p->from.sym->name, p-
 			break;
 		o2 = oshr(p->from.reg, 0, REGTMP, p->scond);
 		break;
-	case 95:	/* PLD reg */
+	case 95:	/* PLD off(reg) */
 		o1 = 0xf5d0f000;
 		o1 |= p->from.reg << 16;
+		if(p->from.offset < 0) {
+			o1 &= ~(1 << 23);
+			o1 |= (-p->from.offset) & 0xfff;
+		} else
+			o1 |= p->from.offset & 0xfff;
 	}
 	
 	out[0] = o1;

src/cmd/5l/optab.c

@@ -232,7 +232,7 @@ Optab	optab[] =
 	{ ALDREXD,	C_SOREG,C_NONE,	C_REG,		91, 4, 0 },
 	{ ASTREXD,	C_SOREG,C_REG,	C_REG,		92, 4, 0 },
 
-	{ APLD,		C_REG,	C_NONE,	C_NONE,		95, 4, 0 },
+	{ APLD,		C_SOREG,C_NONE,	C_NONE,		95, 4, 0 },
 
 	{ AXXX,		C_NONE,	C_NONE,	C_NONE,		 0, 4, 0 },
 };