Commit ace9ff45 authored by Shenghou Ma's avatar Shenghou Ma

sync/atomic: FreeBSD/ARM support

only supports ARMv6K and newer ARM cores.

R=rsc, dave
CC=golang-dev
https://golang.org/cl/6601064
parent ec1ef16c
// Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// FreeBSD/ARM atomic operations.
// TODO(minux): this only supports ARMv6K or higher.
TEXT ·CompareAndSwapInt32(SB),7,$0
B ·CompareAndSwapUint32(SB)
TEXT ·CompareAndSwapUint32(SB),7,$0
B ·armCompareAndSwapUint32(SB)
TEXT ·CompareAndSwapUintptr(SB),7,$0
B ·CompareAndSwapUint32(SB)
TEXT ·CompareAndSwapPointer(SB),7,$0
B ·CompareAndSwapUint32(SB)
TEXT ·AddInt32(SB),7,$0
B ·AddUint32(SB)
TEXT ·AddUint32(SB),7,$0
B ·armAddUint32(SB)
TEXT ·AddUintptr(SB),7,$0
B ·AddUint32(SB)
TEXT ·CompareAndSwapInt64(SB),7,$0
B ·CompareAndSwapUint64(SB)
TEXT ·CompareAndSwapUint64(SB),7,$-4
B ·armCompareAndSwapUint64(SB)
TEXT ·AddInt64(SB),7,$0
B ·addUint64(SB)
TEXT ·AddUint64(SB),7,$0
B ·addUint64(SB)
TEXT ·LoadInt32(SB),7,$0
B ·LoadUint32(SB)
TEXT ·LoadUint32(SB),7,$0
MOVW addr+0(FP), R1
load32loop:
LDREX (R1), R2 // loads R2
STREX R2, (R1), R0 // stores R2
CMP $0, R0
BNE load32loop
MOVW R2, val+4(FP)
RET
TEXT ·LoadInt64(SB),7,$0
B ·loadUint64(SB)
TEXT ·LoadUint64(SB),7,$0
B ·loadUint64(SB)
TEXT ·LoadUintptr(SB),7,$0
B ·LoadUint32(SB)
TEXT ·LoadPointer(SB),7,$0
B ·LoadUint32(SB)
TEXT ·StoreInt32(SB),7,$0
B ·StoreUint32(SB)
TEXT ·StoreUint32(SB),7,$0
MOVW addr+0(FP), R1
MOVW val+4(FP), R2
storeloop:
LDREX (R1), R4 // loads R4
STREX R2, (R1), R0 // stores R2
CMP $0, R0
BNE storeloop
RET
TEXT ·StoreInt64(SB),7,$0
B ·storeUint64(SB)
TEXT ·StoreUint64(SB),7,$0
B ·storeUint64(SB)
TEXT ·StoreUintptr(SB),7,$0
B ·StoreUint32(SB)
TEXT ·StorePointer(SB),7,$0
B ·StoreUint32(SB)
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