Commit c2801265 authored by Michael Munday's avatar Michael Munday Committed by Michael Munday

cmd/asm, cmd/internal/obj/s390x, math: add "test under mask" instructions

Adds the following s390x test under mask (immediate) instructions:

TMHH
TMHL
TMLH
TMLL

These are useful for testing bits and are already used in the math package.

Change-Id: Idffb3f83b238dba76ac1e42ac6b0bf7f1d11bea2
Reviewed-on: https://go-review.googlesource.com/41092
Run-TryBot: Michael Munday <mike.munday@ibm.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: 's avatarCherry Zhang <cherryyz@google.com>
parent 96cdacb9
......@@ -213,6 +213,11 @@ TEXT main·foo(SB),DUPOK|NOSPLIT,$16-0 // TEXT main.foo(SB), DUPOK|NOSPLIT, $16-
CMPWU R1, R2 // 1512
CMPWU R3, $4294967295 // c23fffffffff
TMHH R1, $65535 // a712ffff
TMHL R2, $1 // a7230001
TMLH R3, $0 // a7300000
TMLL R4, $32768 // a7418000
BNE 0(PC) // a7740000
BEQ 0(PC) // a7840000
BLT 0(PC) // a7440000
......
......@@ -327,6 +327,12 @@ const (
ACMPW
ACMPWU
// test under mask
ATMHH
ATMHL
ATMLH
ATMLL
// compare and swap
ACS
ACSG
......
......@@ -112,6 +112,10 @@ var Anames = []string{
"CMPU",
"CMPW",
"CMPWU",
"TMHH",
"TMHL",
"TMLH",
"TMLL",
"CS",
"CSG",
"SYNC",
......
......@@ -252,6 +252,9 @@ var optab = []Optab{
Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0},
Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0},
// test under mask
Optab{ATMHH, C_REG, C_NONE, C_NONE, C_ANDCON, 91, 0},
// 32-bit access registers
Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0},
Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0},
......@@ -951,6 +954,10 @@ func buildop(ctxt *obj.Link) {
opset(ACMPW, r)
case ACMPU:
opset(ACMPWU, r)
case ATMHH:
opset(ATMHL, r)
opset(ATMLH, r)
opset(ATMLL, r)
case ACEFBRA:
opset(ACDFBRA, r)
opset(ACEGBRA, r)
......@@ -3704,6 +3711,20 @@ func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(c.regoff(p.GetFrom3())), asm)
}
case 91: // test under mask (immediate)
var opcode uint32
switch p.As {
case ATMHH:
opcode = op_TMHH
case ATMHL:
opcode = op_TMHL
case ATMLH:
opcode = op_TMLH
case ATMLL:
opcode = op_TMLL
}
zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm)
case 93: // GOT lookup
v := c.vregoff(&p.To)
if v != 0 {
......
......@@ -110,7 +110,7 @@ L2:
WFMDB V1, V1, V2
LGDR F3, R1
MOVD $sincosxlim<>+0(SB), R2
WORD $0xA7110001 //tmll %r1,1
TMLL R1, $1
BEQ L6
FMOVD 0(R2), F0
WFCHDBS V0, V5, V0
......@@ -134,7 +134,7 @@ L2:
WFMADB V2, V0, V3, V0
FMOVD 0(R2), F6
WFMADB V1, V4, V6, V4
WORD $0xA7110002 //tmll %r1,2
TMLL R1, $2
WFMADB V2, V0, V4, V0
MOVD $sincosc0<>+0(SB), R1
FMOVD 0(R1), F2
......@@ -170,7 +170,7 @@ L6:
FNEG F6, F4
WFMADB V2, V0, V3, V2
WFMDB V4, V1, V0
WORD $0xA7110002 //tmll %r1,2
TMLL R1, $2
WFMSDB V0, V2, V6, V0
BNE L15
FMOVD F0, ret+8(FP)
......@@ -261,7 +261,7 @@ L21:
FMOVD 0(R2), F5
WFMDB V2, V2, V6
MOVD $sincosxlim<>+0(SB), R2
WORD $0xA7110001 //tmll %r1,1
TMLL R1, $1
BNE L25
FMOVD 0(R2), F0
WFCHDBS V0, V1, V0
......@@ -285,7 +285,7 @@ L21:
WFMADB V6, V0, V3, V0
FMOVD 0(R2), F1
WFMADB V2, V4, V1, V4
WORD $0xA7110002 //tmll %r1,2
TMLL R1, $2
WFMADB V6, V0, V4, V0
MOVD $sincosc0<>+0(SB), R1
FMOVD 0(R1), F4
......@@ -320,7 +320,7 @@ L25:
FMADD F3, F2, F1
FMUL F0, F2
WFMADB V6, V4, V1, V6
WORD $0xA7110002 //tmll %r1,2
TMLL R1, $2
FMADD F6, F2, F0
BNE L34
FMOVD F0, ret+8(FP)
......
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