Commit d186d07e authored by Shenghou Ma's avatar Shenghou Ma

cmd/5a, cmd/5l, math: add CLZ instruction for ARM

        Supported in ARMv5 and above.

R=golang-dev, rsc
CC=golang-dev
https://golang.org/cl/6284043
parent 65e61d57
......@@ -406,6 +406,8 @@ struct
"PLD", LTYPEPLD, APLD,
"UNDEF", LTYPEE, AUNDEF,
"CLZ", LTYPE2, ACLZ,
0
};
......
......@@ -184,9 +184,11 @@ enum as
ASTREXD,
APLD,
AUNDEF,
ACLZ,
ALAST,
};
......
......@@ -1801,6 +1801,11 @@ if(debug['G']) print("%ux: %s: arm %d\n", (uint32)(p->pc), p->from.sym->name, p-
o1 = opbra(ABL, C_SCOND_NONE);
o1 |= (v >> 2) & 0xffffff;
break;
case 97: /* CLZ Rm, Rd */
o1 = oprrr(p->as, p->scond);
o1 |= p->to.reg << 12;
o1 |= p->from.reg;
break;
}
out[0] = o1;
......@@ -1958,6 +1963,10 @@ oprrr(int a, int sc)
return o | (0xe<<24) | (0x1<<20) | (0xb<<8) | (1<<4);
case ACMP+AEND: // cmp imm
return o | (0x3<<24) | (0x5<<20);
case ACLZ:
// CLZ doesn't support .S
return (o & (0xf<<28)) | (0x16f<<16) | (0xf1<<4);
}
diag("bad rrr %d", a);
prasm(curp);
......
......@@ -236,5 +236,7 @@ Optab optab[] =
{ AUNDEF, C_NONE, C_NONE, C_NONE, 96, 4, 0 },
{ ACLZ, C_REG, C_NONE, C_REG, 97, 4, 0 },
{ AXXX, C_NONE, C_NONE, C_NONE, 0, 4, 0 },
};
......@@ -848,6 +848,7 @@ buildop(void)
case ATST:
case APLD:
case AUNDEF:
case ACLZ:
break;
}
}
......
......@@ -314,7 +314,7 @@ TEXT ·mulWW(SB),7,$0
// func bitLen(x Word) (n int)
TEXT ·bitLen(SB),7,$0
MOVW x+0(FP), R0
WORD $0xe16f0f10 // CLZ R0, R0 (count leading zeros)
CLZ R0, R0
MOVW $32, R1
SUB.S R0, R1
MOVW R1, n+4(FP)
......
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