Fixes VBLENDVP{D/S}, VPBLENDVB encoding for /is4 imm8[7:4]
encoded register operand.

Explanation:
`reg[r]+regrex[r]+1` will yield correct values for 8..15 reg indexes,
but for 0..7 it gives `index+1` results.
There was no test that used lower 8 register with /is4 encoding,
so the bug passed the tests.
The proper solution is to get 4th bit from regrex with a proper shift:
`reg[r]|(regrex[r]<<1)`.

Instead of inlining `reg[r]|(regrex[r]<<1)` expr,
using new `regIndex(r)` function.

Test that reproduces this issue is added to
amd64enc_extra.s test suite.

Bug came from https://golang.org/cl/70650.

Change-Id: I846a25e88d5e6df88df9d9c3f5fe94ec55416a33
Reviewed-on: https://go-review.googlesource.com/78815
Run-TryBot: Iskander Sharipov <iskander.sharipov@intel.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Ilya Tocar <ilya.tocar@intel.com>